1. Field of the Invention
The present invention relates to a system for improving processing performance in a computer employing two or more bus architectures or employing a hierarchical bus structure.
2. Description of Prior Art
Over the past ten years, advances in microprocessor technology have enabled personal computers to achieve increasingly higher levels of performance. Software applications have also become much more complex and sophisticated during this same time period. Today's software involves sophisticated graphics, on-line transaction processing, local-area networking and real-time video. These relatively new applications require vast amounts of data to be processed and moved faster than ever before between a microcomputer computer's central processing unit (CPU) and peripheral units. The industry-standard 16-bit/8-MHz ISA (Industry Standard Architecture) expansion bus--the decade-old bus found in most computers today--cannot adequately transport the large amounts of data generated by these applications. The ISA expansion bus, introduced in 1984 by IBM, forces today's high-performance 32-bit microprocessors to wait as hard disks, video boards and other peripherals send and receive data along a path that is narrow, slow, and inefficient. Consequently, serious bottlenecks occur in modern microprocessor-based systems, operating at 66 MHz and faster, as applications using large files vie for the precious limited bandwidth offered by the ISA system bus.
Enhanced bus standards that have been introduced in an attempt to replace ISA, such as Extended Industry Standard Architecture (EISA) and Micro Channel Architecture (MCA), improve data throughput and provide capability for short bursts as fast as 33 MBps with EISA and potentially faster with MCA. But limited availability, design complexity, and high production costs have relegated these solutions to servers and specialized systems.
Today's solution to the bottleneck problem is generally acknowledged to be an innovation called the local bus. The bus is "local" in the sense that it brings peripheral functions closer to the microprocessor. The CPU bus provides a high speed data path that traditionally has been reserved for the CPU, cache and main memory subsystem. The expansion bus, by comparison, provides the lower speed data path and physical connection between all peripherals and the CPU bus. With the addition of a local bus, peripherals that require rapid transfers of large amounts of data are put in close connection with the CPU and memory subsystem. This arrangement allows high-performance peripherals such as video cards, network adapters and disk controllers to bypass the I/O bottlenecks of traditional system buses and take a short cut to the CPU. In a 486 DX2-66 CPU-based system, for example, the local bus is 32 bits wide and runs at 33 MHz for bus throughput as fast as 132 MBps.
Not all peripherals require high data transfer rates in order to perform up to their potential. Lower-bandwidth peripherals such as FAX/modems, tape drives and printers are still well served by the standard ISA expansion bus. Because of this, local bus systems are usually designed in conjunction with an ISA expansion bus. In a typical local bus implementation, the ISA expansion bus controller feeds into the local bus as though it were another peripheral, providing the interface for lower performance add-in cards that are configured within the system. Computing systems therefore often involve multiple bus architectures and a bus hierarchy. FIG. 1 shows a typical PC with a bus hierarchy. Both a local bus 10 and an ISA expansion bus 11 are shown. A graphics controller 12 and monitor 13 reside on the local bus, along with an IDE hard drive controller 14 and hard disk 15. A fax modem 16 resides on the ISA expansion bus. The bus structure of FIG. 1 is hierarchical since the local bus is typically accessed first to utilize its speed. The ISA bus is addressed only after the addressed device is determined not to be on the local bus.
A number of manufactures (e.g., Dell, NEC, Hewlett-Packard) have developed proprietary local bus systems, most of which integrate local bus video on the motherboard. But there are two emerging local bus standards: (1) the VESA local bus (or VL bus), developed by the Video Electronics Standards Association, and (2) the Peripheral Component Interconnect standard, developed by Intel as a high-end alternative to the VL bus. Both of these standards make available standardized slots into which one can plug high-speed local bus peripherals. FIG. 2 shows the bus architecture for a PC with a CPU host bus 21, both VL and PCI local busses (22 and 23, respectively), and an ISA expansion bus 24.
FIG. 2 also shows a CPU device 31, and a main memory device 32. The busses in FIG. 2 are hierarchical, and the VL bus 22 is deemed to have a higher priority than the PCI bus 23, which has a higher priority than the ISA bus 24. When an I/O cycle is started in FIG. 2, the I/O address is decoded by a subtractive decoding scheme; i.e., by placing it on each of the busses until a device responds. Following this hierarchical order, the bus cycle operation is initiated first on the VL bus, and the CPU waits for a response from that bus (in the VL-bus context, this response is the "local device" or "LDEV" signal). Such a signal indicates that the address corresponds to a device on the VL-bus, and upon receipt, a bus operation is carried out on the VL-bus. If, however, no VL-bus device responds after a number of clock cycles (typically three or four clock cycles), it is assumed that the addressed device is not connected to the VL-bus. No bus operation is carried out on the VL-bus in this situation, and the address is issued next to the PCI bus. If the address corresponds to a device on the PCI bus, the PCI bus responds with "device select" signal ("DEVSEL"). Again, however, if no device responds after a number of clock cycles, the address is then issued to the next bus in the hierarchical order (the ISA bus).
This subtractive decoding scheme for multiple or hierarchical bus structures is inefficient and slow because a number of clock cycles can be expended waiting for a response from each bus. Yet the higher throughput afforded by local bus architectures are necessary for today's software, and hierarchical bus architectures have become the microcomputing norm. What is needed, therefore, is a method or apparatus for reducing delays introduced by the slow decoding schemes used in today's computers, while still providing the functionality and utility of multiple and hierarchical bus architecture.